Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Reading design: /home/keshi/svn/logic/crtc00/current/crtc.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "/home/keshi/svn/logic/crtc00/current/crtc.prj" Input Format : mixed ---- Target Parameters Output File Name : "crtc" Output Format : ngc Target Device : xc3s200-ft256-4 ---- Source Options Top Module Name : crtc ---- Other Options verilog2001 : YES ========================================================================= WARNING:Xst:29 - Optimization Effort not specified The following parameters have been added: Optimization Goal : SPEED Optimization Effort : 1 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "/home/keshi/svn/logic/crtc00/current/crtc.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:1537 - "/home/keshi/svn/logic/crtc00/current/crtc.vhd" line 44: Generic of type Time is ignored. WARNING:Xst:1537 - "/home/keshi/svn/logic/crtc00/current/crtc.vhd" line 44: Generic of type Time is ignored. WARNING:Xst:1537 - "/home/keshi/svn/logic/crtc00/current/crtc.vhd" line 21723: Generic of type Time is ignored. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "/home/keshi/svn/logic/crtc00/current/crtc.vhd". WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 1-bit register for signal . Found 1-bit register for signal . Found 10-bit up counter for signal . Found 10-bit up counter for signal . Found 6-bit subtractor for signal . Found 6-bit adder for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Counter(s). inferred 4 D-type flip-flop(s). inferred 2 Adder/Subtractor(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 2 6-bit adder : 1 6-bit subtractor : 1 # Counters : 2 10-bit up counter : 2 # Registers : 4 1-bit register : 4 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Loading device for application Rf_Device from file '3s200.nph' in environment /home/keshi/Xilinx. Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... ========================================================================= * Final Report * ========================================================================= Final Results Top Level Output File Name : crtc Output Format : ngc Optimization Goal : SPEED Keep Hierarchy : no Design Statistics # IOs : 6 Macro Statistics : # Registers : 4 # 1-bit register : 4 # Counters : 2 # 10-bit up counter : 2 # Adders/Subtractors : 2 # 6-bit adder : 1 # 6-bit subtractor : 1 Cell Usage : # BELS : 113 # GND : 1 # INV : 4 # LUT1 : 10 # LUT2 : 15 # LUT2_L : 2 # LUT3 : 4 # LUT3_L : 2 # LUT4 : 9 # LUT4_D : 4 # LUT4_L : 9 # MUXCY : 30 # VCC : 1 # XORCY : 22 # FlipFlops/Latches : 24 # FDCE : 2 # FDCPE : 20 # FDPE : 2 # Clock Buffers : 2 # BUFG : 2 # IO Buffers : 6 # IBUFG : 1 # OBUF : 5 # DCMs : 1 # DCM : 1 # Others : 1 # ROC : 1 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 29 out of 1920 1% Number of Slice Flip Flops: 24 out of 3840 0% Number of 4 input LUTs: 55 out of 3840 1% Number of bonded IOBs: 6 out of 173 3% Number of GCLKs: 2 out of 8 25% Number of DCM_ADVs: 1 out of 4 25% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLK | DCM0:CLKDV | 24 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 4.009ns (Maximum Frequency: 249.439MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 12.056ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'CLK' Clock period: 4.009ns (frequency: 249.439MHz) Total number of paths / destination ports: 1014 / 38 ------------------------------------------------------------------------- Delay: 8.018ns (Levels of Logic = 4) Source: CH_2 (FF) Destination: IV (FF) Source Clock: CLK rising 0.5X Destination Clock: CLK rising 0.5X Data Path: CH_2 to IV Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCPE:C->Q 5 0.720 1.260 CH_2 (CH_2) LUT4_L:I0->LO 1 0.551 0.126 _n0014_SW0_SW0 (N70) LUT4:I3->O 8 0.551 1.109 _n0014_SW0 (N131) LUT4_D:I3->O 13 0.551 1.196 _n0014 (_n0014) LUT4:I3->O 1 0.551 0.801 _n0012 (_n0012) FDCE:CE 0.602 BH ---------------------------------------- Total 8.018ns (3.526ns logic, 4.492ns route) (44.0% logic, 56.0% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK' Total number of paths / destination ports: 43 / 5 ------------------------------------------------------------------------- Offset: 12.056ns (Levels of Logic = 9) Source: CH_0 (FF) Destination: VG (PAD) Source Clock: CLK rising 0.5X Data Path: CH_0 to VG Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDCPE:C->Q 5 0.720 1.260 CH_0 (CH_0) LUT2:I0->O 1 0.551 0.000 crtclut5 (N10) MUXCY:S->O 1 0.500 0.000 crtccy_rn_4 (crtc_cyo5) MUXCY:CI->O 1 0.064 0.000 crtccy_rn_5 (crtc_cyo6) MUXCY:CI->O 1 0.064 0.000 crtccy_rn_6 (crtc_cyo7) MUXCY:CI->O 1 0.064 0.000 crtccy_rn_7 (crtc_cyo8) MUXCY:CI->O 0 0.064 0.000 crtccy_rn_8 (crtc_cyo9) XORCY:CI->O 1 0.904 0.869 crtc_HMV<5>_xor (HMV<5>) LUT3:I2->O 1 0.551 0.801 VG1 (VG_OBUF) OBUF:I->O 5.644 VG_OBUF (VG) ---------------------------------------- Total 12.056ns (9.126ns logic, 2.930ns route) (75.7% logic, 24.3% route) ========================================================================= CPU : 2.94 / 5.28 s | Elapsed : 3.00 / 3.00 s --> Total memory usage is 87828 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 6 ( 0 filtered) Number of infos : 0 ( 0 filtered)